// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VRISCV_BOARD.h for the primary calling header

#include "verilated.h"
#include "verilated_dpi.h"

#include "VRISCV_BOARD___024root.h"

VL_INLINE_OPT void VRISCV_BOARD___024root___ico_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___ico_sequent__TOP__0\n"); );
    // Body
    vlSelf->RISCV_BOARD__DOT__inst_sram_en = ((~ (IData)(vlSelf->reset)) 
                                              & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin));
}

void VRISCV_BOARD___024root___eval_ico(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_ico\n"); );
    // Body
    if (vlSelf->__VicoTriggered.at(0U)) {
        VRISCV_BOARD___024root___ico_sequent__TOP__0(vlSelf);
    }
}

VL_INLINE_OPT void VRISCV_BOARD___024root___act_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___act_sequent__TOP__0\n"); );
    // Init
    CData/*31:0*/ __Vtemp_h37e7e4c0__0;
    // Body
    __Vtemp_h37e7e4c0__0 = (((0x1bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                             << 4U) | ((((((((0xc0U 
                                              == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                             | (0xc1U 
                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                            | (0xc5U 
                                               == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                           | (0xc7U 
                                              == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                          | (0xc4U 
                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                         | (0xc6U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                        << 3U) | ((
                                                   (((0x40U 
                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                     | (0x41U 
                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                    | (0x42U 
                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                   << 2U) 
                                                  | ((((5U 
                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                       | (0xdU 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op))) 
                                                      << 1U) 
                                                     | (1U 
                                                        & (~ (IData)(
                                                                     (0U 
                                                                      != 
                                                                      (0xfU 
                                                                       & ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel) 
                                                                          >> 1U))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel 
        = __Vtemp_h37e7e4c0__0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm 
        = ((1U & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel))
            ? (((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0))) 
                << 0xcU) | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                             ? 0U : (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                     >> 0x14U))) : 
           ((2U & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel))
             ? (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                  ? 0U : (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                          >> 0xcU)) << 0xcU) : ((4U 
                                                 & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel))
                                                 ? 
                                                (((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0))) 
                                                  << 0xcU) 
                                                 | ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                       ? 0U
                                                       : 
                                                      (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                       >> 0x19U)) 
                                                     << 5U) 
                                                    | (IData)(vlSelf->__VdfgTmp_hea37eb48__0)))
                                                 : 
                                                ((8U 
                                                  & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel))
                                                  ? 
                                                 (((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0))) 
                                                   << 0xcU) 
                                                  | ((0x800U 
                                                      & (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
                                                          << 0xbU) 
                                                         & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                            << 4U))) 
                                                     | ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                           ? 0U
                                                           : 
                                                          (0x3fU 
                                                           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                              >> 0x19U))) 
                                                         << 5U) 
                                                        | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                             ? 0U
                                                             : 
                                                            (0xfU 
                                                             & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                                >> 8U))) 
                                                           << 1U))))
                                                  : 
                                                 (((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0))) 
                                                   << 0x14U) 
                                                  | ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                        ? 0U
                                                        : 
                                                       (0xffU 
                                                        & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                           >> 0xcU))) 
                                                      << 0xcU) 
                                                     | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak) 
                                                         << 0xbU) 
                                                        | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                             ? 0U
                                                             : 
                                                            (0x3ffU 
                                                             & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                                >> 0x15U))) 
                                                           << 1U))))))));
    vlSelf->RISCV_BOARD__DOT__inst_sram_addr = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass)
                                                 ? 
                                                ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                                                  ? 
                                                 ((1U 
                                                   & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                   ? 
                                                  vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[0U]
                                                   : 
                                                  (((1U 
                                                     & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                     ? 0U
                                                     : 
                                                    ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                                                      << 0x1eU) 
                                                     | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U] 
                                                        >> 2U))) 
                                                   + 
                                                   ((1U 
                                                     & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                     ? 0U
                                                     : 
                                                    ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                      << 0x1cU) 
                                                     | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                                                        >> 4U)))))
                                                  : 
                                                 ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0)
                                                   ? 
                                                  (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U] 
                                                   + vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm)
                                                   : 
                                                  (0xfffffffeU 
                                                   & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 
                                                      + vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm))))
                                                 : 
                                                ((IData)(4U) 
                                                 + vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc));
}

void VRISCV_BOARD___024root___eval_act(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_act\n"); );
    // Body
    if (vlSelf->__VactTriggered.at(0U)) {
        VRISCV_BOARD___024root___act_sequent__TOP__0(vlSelf);
    }
}

void VRISCV_BOARD___024root___nba_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf);

void VRISCV_BOARD___024root___eval_nba(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_nba\n"); );
    // Body
    if (vlSelf->__VnbaTriggered.at(1U)) {
        VRISCV_BOARD___024root___nba_sequent__TOP__0(vlSelf);
    }
    if ((vlSelf->__VnbaTriggered.at(0U) | vlSelf->__VnbaTriggered.at(1U))) {
        VRISCV_BOARD___024root___act_sequent__TOP__0(vlSelf);
    }
}

void VRISCV_BOARD___024root___eval_triggers__ico(VRISCV_BOARD___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__ico(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG
void VRISCV_BOARD___024root___eval_triggers__act(VRISCV_BOARD___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__act(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG
#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__nba(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG

void VRISCV_BOARD___024root___eval(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval\n"); );
    // Init
    CData/*0:0*/ __VicoContinue;
    VlTriggerVec<2> __VpreTriggered;
    IData/*31:0*/ __VnbaIterCount;
    CData/*0:0*/ __VnbaContinue;
    // Body
    vlSelf->__VicoIterCount = 0U;
    __VicoContinue = 1U;
    while (__VicoContinue) {
        __VicoContinue = 0U;
        VRISCV_BOARD___024root___eval_triggers__ico(vlSelf);
        if (vlSelf->__VicoTriggered.any()) {
            __VicoContinue = 1U;
            if (VL_UNLIKELY((0x64U < vlSelf->__VicoIterCount))) {
#ifdef VL_DEBUG
                VRISCV_BOARD___024root___dump_triggers__ico(vlSelf);
#endif
                VL_FATAL_MT("/home/finalx/ysyx-workbench/npc/vsrc/RISCV_BOARD.v", 3, "", "Input combinational region did not converge.");
            }
            vlSelf->__VicoIterCount = ((IData)(1U) 
                                       + vlSelf->__VicoIterCount);
            VRISCV_BOARD___024root___eval_ico(vlSelf);
        }
    }
    __VnbaIterCount = 0U;
    __VnbaContinue = 1U;
    while (__VnbaContinue) {
        __VnbaContinue = 0U;
        vlSelf->__VnbaTriggered.clear();
        vlSelf->__VactIterCount = 0U;
        vlSelf->__VactContinue = 1U;
        while (vlSelf->__VactContinue) {
            vlSelf->__VactContinue = 0U;
            VRISCV_BOARD___024root___eval_triggers__act(vlSelf);
            if (vlSelf->__VactTriggered.any()) {
                vlSelf->__VactContinue = 1U;
                if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) {
#ifdef VL_DEBUG
                    VRISCV_BOARD___024root___dump_triggers__act(vlSelf);
#endif
                    VL_FATAL_MT("/home/finalx/ysyx-workbench/npc/vsrc/RISCV_BOARD.v", 3, "", "Active region did not converge.");
                }
                vlSelf->__VactIterCount = ((IData)(1U) 
                                           + vlSelf->__VactIterCount);
                __VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered);
                vlSelf->__VnbaTriggered.set(vlSelf->__VactTriggered);
                VRISCV_BOARD___024root___eval_act(vlSelf);
            }
        }
        if (vlSelf->__VnbaTriggered.any()) {
            __VnbaContinue = 1U;
            if (VL_UNLIKELY((0x64U < __VnbaIterCount))) {
#ifdef VL_DEBUG
                VRISCV_BOARD___024root___dump_triggers__nba(vlSelf);
#endif
                VL_FATAL_MT("/home/finalx/ysyx-workbench/npc/vsrc/RISCV_BOARD.v", 3, "", "NBA region did not converge.");
            }
            __VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
            VRISCV_BOARD___024root___eval_nba(vlSelf);
        }
    }
}

#ifdef VL_DEBUG
void VRISCV_BOARD___024root___eval_debug_assertions(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_debug_assertions\n"); );
    // Body
    if (VL_UNLIKELY((vlSelf->clk & 0xfeU))) {
        Verilated::overWidthError("clk");}
    if (VL_UNLIKELY((vlSelf->reset & 0xfeU))) {
        Verilated::overWidthError("reset");}
}
#endif  // VL_DEBUG
